1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to memory devices with an improved ROM code region.
2. Description of Related Art
FIG. 1 is a schematic plan view of a prior art ROM device comprising a semiconductor substrate coated with a gate oxide layer 15, with an array of bit lines BL1 and BL2 and with an array of word lines WL1, WL2, and WL3 passing over the tops of the bit lines BL1 and BL2. A ROM code implant region 14 is located within the space under a particular word line WL2 at its intersection with two adjacent bit lines BL1 and BL2.
The problem with the prior art process of FIG. 1 is that the side diffusion of dopant from ROM code implant 14 causes extension into the non-active area between the particular word line WL2 (where the ROM code location belongs) and adjacent word lines WL1 and WL3, as shown in FIG. 1.